An FPU design template to optimize the accuracy-efficiency-area trade-off

Modern embedded systems are in charge of an increasing number tasks that extensively employ floating-point (FP) computations. The ever-increasing efficiency requirement, coupled with the additional computational effort to perform FP computations, motivates several microarchitectural optimizations FPU. This manuscript presents a novel modular FPU microarchitecture, which targets modern and considers heterogeneous workloads including both best-effort accuracy-sensitive applications. design optimizes EDP-accuracy-area figure merit by allowing, at design-time, independently configure precision each operation, while dynamic range is kept common entire deliver simpler microarchitecture. To ensure correct execution applications, compiler pass allows substitute operation for low-precision hardware support offered corresponding soft-float function call. assessment seven variants encompassing three different state-of-the-art designs. results on representative use cases show binary32 implementation offers EDP gain 15%, while, case implements mix bfloat16 operations, 19%, reduction resource utilization 21% average accuracy loss less than 2.5%. Moreover, our aligned one employing state-of-the-art, highly specialized accelerators. Starting from assessment, set guidelines drawn steer systems.